A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs

A core operation in actual circuits, especially in digital signal processing algorithms, is multiplication. Often, the computational performance of a DSP system is limited by its multiplication performance [Pet95]. The implementation of multiplier modules into FPGAs is crucial in terms of area, speed and pin limitation. In many cases, even small multiplier modules will exceed the capacity of one FPGA. In traditional design flows, the RTL modules must then be converted to a flat CLB netlist and be partitioned into multiple FPGA chips. Since the partitioning step is mainly constrained by FPGA pin limitation, this often results in solutions with very low logic utilization [Fan96]. This becomes a key problem, especially in the case of logic emulation systems [But92], since each FPGA has to provide several IOs for debugging purposes. Note, that the application of such a prototyping system can be restricted either by its limited FPGA count or by high clock rate demands. Therefore, the optimization goal during implementation can be either minimum area or minimum delay. In this paper, a new approach to implement fast array multipliers of any word length in SRAM-based FPGAs is presented. The proposed method is based on a generic FPGA model and, therefore, suitable for most commercial FPGA devices. Taking the logical structure of the multiplier into account, technology mapping including adaptive structure generation as well as signal flow driven placement and automatic partitioning are efficiently performed yielding implementations of higher performance and better resource utilization as published before.